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../../../../build/ip/xilinx/bram64k_64x1024_xilinx/sim/bram64k_64x1024_xilinx.v
../../../../build/ip/xilinx/bram2m_xilinx/simulation/blk_mem_gen_v8_4.v
../../../../build/ip/xilinx/bram2m_xilinx/sim/bram2m_xilinx.v
../../3RD_PARTY_IP/rtl/altera_mf.v
../../../../verilog/bram64k.v
../../../../verilog/bank64k.v
../../../../verilog/bram2m.v
../../../../verilog/cdru.v
../../../../verilog/cdwu.v
../../../../verilog/maxpool.v
../../../../verilog/mvp.v
../../../../verilog/mvu.v
../../../../verilog/shacc.v
../../../../verilog/vvp.v
../../../../verilog/interconn.v
../../../../verilog/quantser.v
../../../../verilog/quantser_ctrl.v
../../../../verilog/outagu.v
../../../../verilog/inagu.sv
../../../../verilog/agu.sv
../../../../verilog/zigzagu.v
../../../../verilog/controller.v
../../../../verilog/shiftreg.v
../../../../verilog/fixedpointscaler.v
../../../../verilog/mvutop.sv
../../../lib/utils/utils.sv
../tb/mvutop_tester.sv